The present invention relates to semiconductor devices, and, more particularly, to semiconductor trench structures having fill material of, e.g., silicon or polycrystalline silicon.
Semiconductor devices are employed in various systems for a wide variety of applications. Device fabrication typically involves a series of process steps including layering materials on a semiconductor substrate wafer, patterning and etching one or more of the material layers, doping selected layers and cleaning the wafer.
Semiconductor manufacturers continually seek new ways to improve performance, decrease cost and increase capacity of semiconductor devices. Capacity and cost improvements may be achieved by shrinking device size. For example, in the case of a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) chip, more memory cells can fit onto the chip by reducing the size of memory cell components such as capacitors and transistors. The size reduction results in greater memory capacity for the chip. Cost reduction is achieved through economies of scale. Unfortunately, performance can suffer when device components are shrunk. Therefore, it is a challenge to balance performance with other manufacturing constraints.
One method of shrinking device size is to vertically construct the components, either in a stack over the semiconductor substrate or within the substrate itself. One way to accomplish such vertical construction within the substrate involves forming a trench in the substrate. By way of example only, a capacitor may be fabricated within a trench. Such a capacitor is known as a xe2x80x9ctrench capacitor.xe2x80x9d
The capacitor stores charge and includes a pair of electrodes separated by a dielectric material. The charge can represent a data value for use in a memory cell, such as a DRAM cell. While it is desirable to shrink the surface area of a trench capacitor to increase memory cell density, the trench capacitor must be able to store a sufficient amount of charge. For example, regardless of size, a trench capacitor of a DRAM cell requires a charge on the order of 25-30 fF (femto Farads). Therefore, it is imperative that trench capacitors be able to store sufficient charge. This may be accomplished by creating trenches which extend relatively deep into the substrate.
A conventional trench capacitor is typically formed as follows. First, a trench is etched in the substrate. The trench has sidewalls defined by surrounding portions of the substrate. Then, an outer electrode, a xe2x80x9cburied plate,xe2x80x9d is formed by implanting a dopant in the substrate surrounding the trench. Next, a dielectric liner, the xe2x80x9cnode dielectric,xe2x80x9d is formed along the sidewalls, covering the outer electrode. Subsequently, an inner electrode is deposited within the trench. The inner electrode typically consists of polycrystalline silicon, also known as xe2x80x9cpolysiliconxe2x80x9d or xe2x80x9cpoly-Si.xe2x80x9d
In conventional processing, the trench is formed relatively deep within the substrate. For example, a xe2x80x9cdeep trenchxe2x80x9d may extend between 4-8 xcexcm below the substrate surface at a given stage in the fabrication process. Deep trenches are typically high aspect ratio trenches. The xe2x80x9caspect ratioxe2x80x9d is the ratio of the depth of a trench compared to the width of the opening at the top of the trench. By way of example only, high aspect ratio trenches in advanced semiconductor manufacturing may have an aspect ratio of between 20:1 and 60:1 or higher.
A high aspect ratio trench adversely impacts formation of the inner electrode. This is so because of how the inner electrode is formed. The poly-Si inner electrode is formed by a deposition process such as chemical vapor deposition (xe2x80x9cCVDxe2x80x9d). For example, an ultra high vacuum (xe2x80x9cUHVxe2x80x9d) CVD process may be used, wherein the pressure is below 1xc3x9710xe2x88x927 Torr. During deposition, the poly-Si grows inward from the sidewalls. However, this process typically creates voids, gaps or seams within a central portion of the inner electrode.
FIG. 9 illustrates a conventional trench capacitor 430 having a void 422. A trench 406 has been formed into the substrate 400. A pad stack 402 comprised of a pad oxide 402a and a pad nitride 402b covers the surface of the substrate 400. The sidewalls 404 of the trench 406 extend through the pad stack 402 into the substrate 400. A lower portion of the sidewalls 404 are covered with a node dielectric 410, and an upper portion of the sidewalls 404 are covered by an oxide collar 408. An outer dielectric 412 is formed within the substrate 400 adjacent to the node dielectric 410. An inner electrode 420 of poly-Si is formed within the trench 406. As described above, conventional deposition of the poly-Si typically produces the void 422 (or gap or seam) within the inner electrode 420. The void 422 increases the resistance of the trench capacitor 430, which can adversely affect its performance. Furthermore, the void 422 typically increases the difficulty of later processing of the conventional trench capacitor 430. For example, the poly-Si within the trench 406 may be recessed or etched back to a desired depth below the surface of the substrate 400. The void 422 may render this recessing step unpredictable in terms of, e.g., etch rate, depth and width. If the void 422 is within the etch range during poly-Si recessing or etch-back, e.g., approximately 1.3-1.5 xcexcm below the pad oxide 402a and substrate 400 interface, then the recessing or etch-back depth may become uncontrollable. In such a case, the etching/recessing could leave a prominent xe2x80x9cVxe2x80x9d shape at the bottom of the recessed trench. Then, when the collar 408 is deposited, it could be deposited in the void. Subsequent processing would not remove oxide that remains in the void, which leads to increased contact resistance between the layers of poly-Si deposited to form the inner electrode 420. Furthermore, the presence of the void 422 may create a non-planar surface for the inner electrode 420, thereby affecting later fabrication steps.
Creating a trench having a tapered top can reduce void formation, because the tapered top allows the deposition process better access to the trench, resulting in more complete fill. Generally, increasing the taper angle, e.g., widening the trench opening, reduces void formation. However, larger taper adversely affects the xe2x80x9ceffectivexe2x80x9d trench depth (i.e., the depth of the trench excluding the tapered portion).
A void is revealed by etching through the poly-Si until the void is exposed. The void is typically healed by depositing poly-Si into the void after the collar oxide is formed. However, large voids often cause problems such as poor depth control of the healing deposition process. As such, the deposition of poly-Si within long voids running substantially the depth of the trench may not sufficiently heal the defect.
Thus, new methods of formation of capacitor inner electrodes, as well as formation of other fill materials, are desired. The methods should minimize or eliminate void formation in filled trench structures. Improved methods of healing pre-existing voids are also desired.
The present invention provides methods of forming substantially void-free fillers in trench structures. It is to be appreciated that the numbers used (by way of example only, temperature, time and pressure) are approximations and may be varied, and certain steps may be performed in different order.
In accordance with one embodiment of the present invention, a method of fabricating a semiconductor device is provided. The method comprises first forming a trench having sidewalls in a semiconductor substrate. Next, a liner is deposited over the sidewalls. Then, a filler is grown within the trench from the liner. Preferably, the liner is polysilicon. Also, the filler may be grown in a non-selective manner. Optionally, the method may include removing a native oxide from an exposed surface of the liner prior to growing the filler.
In accordance with another embodiment of the present invention, a method of fabricating a semiconductor device is provided. The method comprises first forming a trench having sidewalls in a semiconductor substrate, and then depositing a first liner over the sidewalls. Next, a second liner is deposited over the first liner. Then, a mask is formed within the trench, and the mask covers a segment of the second liner. Next, portions of the second liner which are not covered by the mask are etched. Then the mask is removed. After removing the mask, portions of the first liner which are not covered by the second liner are then etched. Then remaining portions of the second liner are etched and then a filler is grown within the trench from the first liner that remains. Preferably, the second liner is an oxide, and more preferably is between 5 to 15 nm thick. The method may also include doping the filler by means of in situ doping. This may be performed during the growing step. The step of forming the mask preferably includes first depositing the mask within the trench and then recessing the mask to a desired depth within the trench.
In accordance with yet another embodiment of the present invention, a method of fabricating a semiconductor device is provided. The method comprises first providing a fill material within a trench, wherein the trench has sidewalls formed in a semiconductor substrate. Next, a void within the fill material is exposed. Then, a healing material is grown from the fill material, and the healing material substantially fills the void. Preferably, the healing material is selectively grown from the fill material. More preferably, the healing material is epitaxial silicon.
In accordance with another embodiment of the present invention, a method of fabricating a capacitor is provided. The method comprises first forming a trench having sidewalls in a semiconductor substrate, and forming a buried plate in the semiconductor substrate adjacent to a lower portion of the trench. Next, a dielectric liner is applied along the sidewalls in the lower portion of the trench. Then, a collar is formed along the sidewalls in an upper portion of the trench. A liner is then formed over the sidewalls. Finally, an inner electrode is grown within the trench from the liner. The method preferably also includes a masking process. The masking process comprises the steps of forming a first mask over the liner, depositing a second mask within the trench, wherein the second mask covers a segment of the first mask, removing portions of the first mask which are not covered by the second mask, and removing the second mask, then removing portions of the liner not covered by the first mask, and removing remaining portions of the first mask.